III-V Device with Overlapped Extension Regions Using Replacement Gate

ABSTRACT

A structure and method for fabricating a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) with self-aligned and overlapped extensions using a replacement gate process is disclosed. The a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) structure may be formed by forming a III-V compound semiconductor-containing heterostructure having multiple layers and a T-shaped gate structure using a gate replacement process. The T-shaped gate structure may be formed with a bottom surface substantially below an upper surface of the III-V compound semiconductor-containing heterostructure and an upper surface above the III-V compound semiconductor-containing heterostructure. An undoped region may be formed below the bottom surface of the T-shaped gate structure on a layer of the III-V compound semiconductor-containing heterostructure.

FIELD

The present invention relates generally to the fabrication of integratedcircuits, and more particularly, to a structure and method forfabricating a III-V compound semiconductor-containing heterostructurefield-effect transistor (FET) with self-aligned and overlappedextensions using a replacement gate process.

BACKGROUND

Compound III-V semiconductors are receiving renewed attention for use aschannel materials for advanced ultra large scale integration (ULSI)digital logic applications due to their high electron mobility. Forexample, the InGaAs/InAlAs material system is one of the most promisingmaterial systems for this application due to its large conduction-bandoffsets and high carrier mobility. Schottky-gated InGaAs high electronmobility transistors (HEMTs) grown on InP substrates have producedmaximum transconductance g_(m) values and have been shown to comparefavorably in terms of a power-delay product.

Conventional III-V HEMTs are self-aligned structures in which thephysical length of the gate structure equals the effective length of thechannel. However, in III-V HEMTs, gate leakage due to a lack of gatedielectric is an important factor limiting their performancereliability. Thus, a thin gate dielectric layer is often insertedbetween the gate metal and the wide bandgap barrier layer forming aIII-V metal-oxide semiconductor HEMT (III-V MOS-HEMT) or a III-Vmetal-oxide semiconductor field-effect transistor (III-V MOSFET). Theuse of a gate dielectric layer has the beneficial effect of reducinggate leakage. III-V MOS-HEMTs and III-V MOSFETs devices exhibit aleakage reduction of six to ten orders of magnitude compared to aSchottky barrier HEMT of similar design. However, the use of a gatedielectric has the deleterious effect of reducing the transconductancebecause of a larger gate-to-channel separation. Furthermore, decrease ofgate-to-source capacitance may cause a shift of threshold voltage (Vt)for devices with a doped channel.

One limitation with conventional self-aligned III-V MOS-HEMTs and III-VMOSFETs is that they are typically underlapped (i.e., the effectivelength of the channel is larger than the physical length of the gatestructure) due to the fact that ion implantation techniques used inconventional silicon-based MOSFETs to create overlapped devices are notviable for III-V materials. In III-V devices, damage created from ionimplantation and subsequent rapid thermal anneal (RTA) can lead tostrain relaxation, which degrades the transport properties of III-Vmaterials. Conventional methods to manage the problem of strainrelaxation have involved keeping the RTA temperature low, but this leadsto an insufficient diffusion and insufficient activation of implantedions.

Accordingly, it may be desirable to overcome the deficiencies andlimitations described hereinabove.

SUMMARY

According to one embodiment of the present invention, a method offorming a semiconductor device is disclosed. The method may involveforming of a III-V compound semiconductor-containing heterostructurehaving at least one layer and a T-shaped gate structure using a gatereplacement process. The T-shaped gate structure may be formed with abottom surface substantially below an upper surface of the III-Vcompound semiconductor-containing heterostructure and an upper surfaceabove the III-V compound semiconductor-containing heterostructure. Anundoped region may be formed below the bottom surface of the T-shapedgate structure on a layer of the III-V compound semiconductor-containingheterostructure.

In another embodiment, a method of forming a semiconductor device isdisclosed. The method of forming the semiconductor device may include:forming a III-V compound semiconductor-containing heterostructure havingat least one layer; forming a T-shaped gate structure, having a bottomsurface substantially below an upper surface of the III-V compoundsemiconductor-containing heterostructure and an upper surface above theIII-V compound semiconductor-containing heterostructure, using a gatereplacement process; forming gate spacers, having an outer side that issubstantially flush with an outer side of the T-shaped gate structure,on the upper surface of the III-V compound semiconductor-containingheterostructure adjacent to and contacting a vertical portion of theT-shaped gate structure; forming raised source-drain (RSD) regions onthe upper surface of the III-V compound semiconductor-containingheterostructure adjacent to and contacting the gate spacers; and formingdielectric regions on an upper surface of the RSD regions, thedielectric regions contacting the gate spacers and contacting the outerside of the T-shaped gate structure and having an upper surface that issubstantially flush with the upper surface of the T-shaped gatestructure. An undoped region may be formed below the bottom surface ofthe T-shaped gate structure on a layer of the III-V compoundsemiconductor-containing heterostructure.

In another embodiment, a structure of a semiconductor device isdisclosed. The semiconductor structure may include a III-V compoundsemiconductor-containing heterostructure having at least one layer; aT-shaped gate structure having a bottom surface on a channel layersubstantially below an upper surface of the III-V compoundsemiconductor-containing heterostructure and an upper surface above theIII-V compound semiconductor-containing heterostructure; gate spacers,having an outer side that is substantially flush with an outer side ofthe T-shaped gate structure, on the upper surface of the III-V compoundsemiconductor-containing heterostructure adjacent to and contacting avertical portion of the T-shaped gate structure; and raised source-drain(RSD) regions on the upper surface of the III-V compoundsemiconductor-containing heterostructure adjacent to and contacting thegate spacers. The structure may include dielectric regions on an uppersurface of the RSD regions contacting the gate spacers the outer side ofthe T-shaped gate structure. The dielectric regions may have an uppersurface that is substantially flush with the upper surface of theT-shaped gate structure. The structure may also include an undopedregion below the bottom surface of the T-shaped gate structure on thechannel layer of the III-V compound semiconductor-containingheterostructure.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The following detailed description, given by way of example and notintended to limit the invention solely thereto, will best be appreciatedin conjunction with the accompanying drawings, in which not allstructures may be shown.

FIG. 1 is a cross sectional view of a III-V compoundsemiconductor-containing heterostructure formed on a semiconductorsubstrate, according to an embodiment of the present invention.

FIG. 2 is a cross sectional view illustrating the formation of a dummygate and dummy gate hardmask, according to an embodiment of the presentinvention.

FIG. 3 is a cross sectional view illustrating the formation of sidewallspacers on the vertical sides of the dummy gate and dummy hardmask,according to an embodiment of the present invention.

FIG. 4 is a cross sectional view illustrating the formation of raisedsource-drain (RSD) regions, according to an embodiment of the presentinvention.

FIG. 5 is a cross sectional view illustrating the formation ofdielectric regions on the RSD regions, according to an embodiment of thepresent invention.

FIG. 6 is a cross sectional view illustrating the removal of the dummyhardmask and the dummy gate, according to an embodiment of the presentinvention.

FIG. 7A is a cross sectional view illustrating the removal of an etchstop layer and a barrier layer and formation of a T-shaped gate trench,according to an embodiment of the present invention.

FIG. 7B is a cross sectional view illustrating the formation of a gatedielectric and a gate conductor, according to an embodiment of thepresent invention.

FIG. 8A is a cross sectional view of the formation of an undoped regionat the bottom of the T-shaped gate trench, according to an embodiment ofthe present invention.

FIG. 8B is a cross sectional view of the formation of a gate dielectricand a gate conductor, according to an embodiment of the presentinvention.

The drawings are not necessarily to scale. The drawings are merelyschematic representations, not intended to portray specific parametersof the invention. The drawings are intended to depict only typicalembodiments of the invention. In the drawings, like numbering representslike elements.

DETAILED DESCRIPTION

Detailed embodiments of the claimed structures and methods are disclosedherein; however, it can be understood that the disclosed embodiments aremerely illustrative of the claimed structures and methods that may beembodied in various forms. This invention may, however, be embodied inmany different forms and should not be construed as limited to theexemplary embodiments set forth herein. Rather, these exemplaryembodiments are provided so that this disclosure will be thorough andcomplete and will fully convey the scope of this invention to thoseskilled in the art. In the description and drawings, details ofwell-known features and techniques may be omitted to avoid unnecessarilyobscuring the presented embodiments.

In the following description, numerous specific details are set forth,such as particular structures, components, materials, dimensions,processing steps, and techniques, in order to provide a thoroughunderstanding of the present invention. However, it will be appreciatedby one of ordinary skill of the art that the invention may be practicedwithout these specific details. In other instances, well-knownstructures or processing steps have not been described in detail inorder to avoid obscuring the invention. It will be understood that whenan element as a layer, region, or substrate is referred to as being “on”or “over” another element, it can be directly on the other element orintervening elements may also be present. In contrast, when an elementis referred to as being “directly on” or “directly” over anotherelement, there are no intervening elements present. It will also beunderstood that when an element is referred to as being “beneath” or“under” another element, it can be directly beneath or under the otherelement, or intervening elements may be present. In contrast, when anelement is referred to as being “directly beneath” or “directly under”another element, there are no intervening elements present.

Two embodiments by which to achieve self-aligned overlapped extensionsin a III-V compound semiconductor-containing heterostructure FETs aredescribed in detail below by referring to the accompanying drawingsFIGS. 1-8B. Process steps and structures common to both embodiments aredescribed in detail by FIGS. 1-6, while one embodiment is described indetail by FIGS. 7A-7B and another is described in detail by FIGS. 8A-8B.

In the present invention, the term “III-V compound semiconductor”denotes a semiconductor material that includes at least one element fromGroup III of the Periodic Table of Elements and at least one elementfrom Group V of the Periodic Table of Elements. Typically, each of theIII-V compound semiconductor layers is a binary, ternary, or quaternaryIII-V containing compound. Examples of III-V compound semiconductorsthat can be used in the present invention include, but are not limitedto, alloys of InGaAs, InAlAs, InAlAsSb, InAlAsP, and InGaAsP.

Referring to FIG. 1, an initial structure 100 may be used in oneembodiment of the present invention. Structure 100 may include a III-Vcompound semiconductor-containing heterostructure 101 formed on top of asemiconductor substrate 102. The III-V compound semiconductor-containingheterostructure 101 may include a III-V compound semiconductor bufferlayer 104 having a first bandgap, a III-V compound semiconductor channellayer 106 having a second bandgap located on a upper surface of thebuffer layer 104, a III-V compound semiconductor barrier layer 108having a third bandgap located on an upper surface of the channel layer106, and an etch stop layer 112 on an upper surface of the barrier layer108.

In the present embodiment, the barrier layer 108 may include a deltadoped region 110 that is located in a lower region of the barrier layer108 abutting next to, but not in direct contact with, the interface withthe underlying channel layer 106. The dopant atom present in the deltadoped region 110 may be an n-type dopant (i.e., an element from Group IVor VI of the Periodic Table of Elements) or a p-type dopant (i.e., anelement from Group II or IV of the Periodic Table of Elements). Theconcentration of dopant in the delta doped region 110 may beapproximately 10¹¹ atom/cm² to approximately 10¹³ atom/cm².

The semiconductor substrate 102 may include any semiconductor materialincluding, for example, Si, SiGe, SiGeC, SiC, Ge alloys, Ga, GaAs, InAs,InP, Ge, and all other III-V compound semiconductors. The semiconductorsubstrate 102 may be composed of a layered semiconductor material suchas, for example, a semiconductor-on-insulator substrate. Thesemiconductor substrate 102 may be doped, undoped, or contain doped andundoped regions therein. The semiconductor substrate 102 may have asingle crystal orientation or it may have surface regions that havedifferent crystal orientation. The semiconductor substrate 102 may bestrained, unstrained, or a combination thereof.

The bandgap of the barrier layer 108 (i.e., the third bandgap) may belarger (wider) than the bandgap of the channel layer 106 (i.e., thesecond bandgap). As stated above, the term “bandgap” refers to theenergy difference between the top of the valance band (i.e., E_(v)) andthe bottom of the conduction band (i.e., E_(c)). The barrier layer 108may be composed of a III-V compound semiconductor having a bandgap valuethat is from approximately 0.5 times to approximately 10 times largerthan the bandgap of the III-V compound semiconductor material used inthe channel layer 106. In a preferred embodiment, the barrier layer 108may be composed of a III-V compound semiconductor having a bandgap valuethat is from approximately 1 times to approximately 5 times larger thanthe bandgap of the III-V compound semiconductor material used in thechannel layer 106.

The bandgap of the buffer layer 104 (i.e., the first bandgap) may alsobe larger than that of the channel layer 106. This helps confine theelectrons within the channel layer 106. The buffer layer 104 may becomposed of a III-V compound semiconductor having a bandgap value thatis from approximately 0.5 times to approximately 10 times larger thanthe bandgap of the III-V semiconductor material used in the channellayer 106. In one embodiment, the buffer layer 104 may be composed of aIII-V compound semiconductor having a bandgap value that is fromapproximately 1 times to approximately 5 times larger than the bandgapof the III-V semiconductor material used in the channel layer 106.

It is noted that the bandgap of the buffer layer 104 and the bandgap ofthe barrier layer 108, which are larger than the bandgap of the channellayer 106, do not necessarily have the same value. Since wide bandgapmaterials are used for the barrier layer 108 and buffer layer 104, and anarrow bandgap material is used for the channel layer 106, carriers areconfined to the channel layer 106 under certain gate bias range. Thecarriers may be confined in the channel layer 106 when typical gate biasconditions are applied.

In one embodiment of the present invention, the barrier layer 108 andthe buffer layer 104 may be composed of an alloy of InAlAs, while thechannel layer 106 may be composed of an alloy of InGaAs. By “alloy ofInAlAs” it is meant a composition of In_(x)Al_(1-x)As wherein x is fromapproximately 0 to approximately 1, and more preferably fromapproximately 0.4 to approximately 0.6. By “alloy of InGaAs” it is meanta composition of In_(y)Ga_(1-y)As wherein y is from approximately 0 toapproximately 1, and more preferably from approximately 0.3 toapproximately 0.8. It is noted that each of the III-V compoundsemiconductor layers employed in the present invention may be a singlecrystal material of typical commercial quality. The typical commercialquality of the III-V compound semiconductor layers is a result ofutilizing an epitaxial growth process such as, for example, molecularbeam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD).The III-V compound semiconductor layers may be epitaxially grownutilizing III/V-containing precursors that are well known to thoseskilled in the art. In some embodiments, a graded III-V compoundsemiconductor layer can be formed.

When a delta doped region 110 is formed into the lower region of thebarrier layer 108, an in-situ doping deposition process may be used inwhich the dopant atom is introduced during the initial formation of thebarrier layer 108 and following the formation of a desired thickness ofthe delta doped region 110 (approximately 0.1 nm to approximately 2.0nm), the dopant is removed from the precursor stream and the barrierlayer 108 formation continues. Alternatively, the delta doped region 110may be formed utilizing ion implantation after the barrier layer 108 hasbeen formed. The conditions of such an implant are selected to provide adelta doped region next to, but not in contact with, the interface 107of the underlying channel layer 106.

Each of the individual III-V compound semiconductor layers shown in FIG.1 are thin (providing a total thickness of less than approximately 600nm). The buffer layer 104 may have a thickness of approximately 5 nm toapproximately 500 nm. The channel layer 106 may have a thickness ofapproximately 2 nm to approximately 10 nm. The barrier layer 108 mayhave a thickness of approximately 1 nm to approximately 5 nm. The etchstop layer 112 may have a thickness of approximately 1 nm toapproximately 2 nm.

Referring now to FIG. 2, structure 200 is illustrative of a dummy gate202 and dummy gate hardmask 204 patterned and formed on the III-Vcompound semiconductor-containing heterostructure 101. The dummy gate202 and the dummy gate hardmask 204 may be formed by blanket depositionof a dummy gate layer (not shown) over the etch stop layer 112 and asubsequent blanket deposition of a hardmask layer over the dummy gatelayer (not shown). Standard deposition techniques may be implemented todeposit the dummy gate layer (not shown) such as, but not limited to,chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physicalvapor deposition (PVD), MOCVD, atomic layer deposition (ALD),evaporation, reactive sputtering, chemical solution deposition, or anyother suitable deposition process.

Subsequently, the hardmask layer (not shown) and dummy gate layer (notshown) may be patterned and etched to form the dummy gate 202 and dummygate hardmask 204. In one embodiment, standard masking andphotolithography techniques may be implemented to pattern the dummy gate202 and the dummy gate hardmask 204. In addition, standard etchingtechniques, such as, reactive ion etching (RIE), may then be implementedto etch the dummy gate 202 and the dummy gate hardmask 204 pattern. Thedummy gate 202 may be composed of poly-silicon, an oxide, or a nitride.The dummy gate hardmask 204 may be composed of a nitride, such as, forexample SiN.

Referring now to FIG. 3, a structure 300 shows a pair of sidewallspacers 302 (hereinafter “sidewall spacers”) formed on the verticalsidewalls of the dummy gate 202 and dummy gate hardmask 204. Thesidewall spacers 302 may be composed of the same material at the dummygate hardmask 204. In a preferred embodiment, the sidewall spacers 302may be composed of a nitride. The sidewall spacers 302 may be formed bydepositing a conformal layer of nitride, or by bulk deposition, on theetch stop layer 112, dummy gate 202 and dummy gate hardmask 204 bystandard deposition techniques such as, but not limited to, CVD, PECVD,PVD, MOCVD, ALD, low pressure CVD (LPCVD), evaporation, reactivesputtering, chemical solution deposition, or any other suitabledeposition process. Subsequently, an anisotropic etch, such as RIE, maybe performed to removed the deposited layer from horizontal surfaces ofthe etch stop layer 112 and dummy gate hardmask 204 to form the sidewallspacers 302 on the vertical sidewalls of the dummy gate 202 and thedummy gate hardmask 204.

Referring now to FIG. 4, a structure 400 shows raised source-drain (RSD)regions 402 formed on the etch stop layer 112 adjacent to and contactingthe vertical sides of the sidewall spacers 302. The RSD regions 402 maybe formed by an epitaxial growth process that is selective to the etchstop layer 112 (i.e., does not result in epitaxial growth on the dummygate hardmask 204 and the sidewall spacers 302). As used herein, theterms “epitaxially formed,” “epitaxial growth,” and/or “epitaxialdeposition” mean the growth of a crystalline semiconductor material on adeposition surface. During the epitaxial growth process, chemicalreactants are controlled and system parameters are set so thatdepositing atoms arrive at the deposition surface with sufficient energyto move around on the surface and orient themselves to the crystalarrangement of the atoms of the deposition surface. In one embodiment,the RSD regions 402 may be formed by the epitaxial growth of a III-Vcompound semiconductor. The RSD regions 402 may also be formed by theepitaxial growth of silicon or germanium. In another embodiment, the RSDregions 402 may be composed of SiGe. The RSD regions 402 may have athickness of approximately 5 nm to approximately 30 nm.

In one embodiment, at least one of the RSD regions 402 may be in-situdoped with a p-type dopant during the selective epitaxial growthprocess. P-type semiconductor devices (PFETs) in III-V materials aretypically produced by doping the source-drain regions with a p-typedopant composed of elements from: group II of the Periodic Table ofElements, including beryllium or magnesium, that replace a group IIIatom; or group IV of the Periodic Table of Elements, including carbon,that replace a group V atom. In one embodiment, at least one of the RSDregions 402 may have a p-type dopant in a concentration ranging fromapproximately 1×10¹⁹ atoms/cm³ to approximately 5×10²¹ atoms/cm³. Inanother embodiment, the p-type conductivity dopant may be introduced toat least one of the RSD regions 402 using ion implantation following theepitaxial growth process that is used to form the RSD regions 402.

In one embodiment, at least one of the RSD regions 402 may be in-situdoped with an n-type dopant during the selective epitaxial growthprocess. N-type semiconductor devices (NFETs) in III-V materials aretypically produced by doping the source-drain regions with a dopantcomposed of elements from: group IV of the Periodic Table of Elements,including silicon or germanium, that replace a group III atom; or (ii)group VI of the Periodic Table of Elements, including sulfur, selenium,or tellurium, that replace a group V atom. In one embodiment, at leastone of the RSD regions 402 may have a n-type dopant in a concentrationranging from approximately 1×10¹⁹ atoms/cm³ to approximately 5×10²¹atoms/cm³. In another embodiment, the n-type conductivity dopant may beintroduced to at least one of the RSD regions 402 using ion implantationfollowing the epitaxial growth process that is used to form the RSDregions 402.

Referring now to FIG. 5, a structure 500 shows a pair of dielectricregions 502 (hereinafter “dielectric regions”) formed on an uppersurface of the RSD regions 402 and contacting the vertical sides of thesidewall spacers 302. The dielectric regions 502 may be formed utilizinga conventional deposition process including, but not limited to,depositing dielectric material using molecular beam epitaxy (MBE), CVD,PECVD, ALD, evaporation, physical vapor deposition (PVD), chemicalsolution deposition, and other like deposition processes. The dielectricmaterial may be deposited on the RSD regions 402, the sidewall spacers302, and the dummy gate hardmask 204 using a blanket deposition processand then planarized using a conventional process such as, for example,chemical mechanical planarization (CMP) so an upper surface of thedielectric regions 502 is substantially flush with an upper surface ofthe dummy gate hardmask 204. For this reason, it may be preferable thatthe dielectric regions 502 are composed of a dielectric material havinga composition different than that of the dummy hardmask 204 and sidewallspacers 302.

In an embodiment, the dielectric regions 502 may be composed of a low-kdielectric material including, but not limited to, an oxide and/orsilicates including metal silicates, aluminates, and titanates. A“low-k” material is a dielectric material with a lower dielectricconstant relative to silicon dioxide (SiO₂), which is 3.9 (i.e., theratio of the permittivity of SiO₂ divided by the permittivity of avacuum). In an embodiment in which the dielectric regions 502 arecomposed of an oxide, the oxide may selected from the group including,but not limited to, SiO₂, HfO₂, ZrO₂, Al₂O₃, TiO₂, La₂O₃, SrTiO₃,LaAlO₃, Y₂O₃, and mixtures thereof. In another embodiment, thedielectric regions 502 may be composed of a dielectric material with adielectric constant ranging from approximately 4.0 to approximately 7.0.In such an embodiment, the dielectric regions 502 may be composed of anoxide, including, but not limited to, silicon oxide, carbon dopedsilicon oxide, fluorine doped silicon oxide, hydrogen silsesquioxanepolymer (HSQ), methyl silsesquioxane polymer (MSQ), polyphenyleneoligomer, methyl doped silica, SiO_(x)(CH₃)_(y), SiC_(x)O_(y)H_(y),organosilicate glass (SiCOH), porous SiCOH, and mixtures thereof.

Referring now to FIG. 6, a structure 600 is illustrative of the deviceafter the dummy gate hardmask 204 (FIG. 5), the dummy gate 202 (FIG. 5),and a portion of the sidewall spacers 302 (FIG. 5) have been removed,leaving a pair of gate spacers 602 (hereinafter “gate spacers”) and aT-shaped gate trench 604 exposed. In a preferred embodiment, the dummygate hardmask 204 (FIG. 5), the dummy gate 202 (FIG. 5), and a portionof the sidewall spacers 302 (FIG. 5) may be removed by conventionaletching processes selective to the dielectric regions 502, such as, forexample, RIE. In an embodiment, the etching process used to remove thedummy gate hardmask 204 (FIG. 5), the dummy gate 202 (FIG. 5), and aportion of the sidewall spacers 302 (FIG. 5) stops before and does notaffect the etch stop layer 112.

Referring now to FIG. 7A, the etch stop layer 112 (FIG. 6) and theentirety of the barrier layer 108, including the delta doped region 110,may be removed from the portion of the T-shaped gate trench 604 notcovered by the gate spacers 602 to form a T-shaped gate region 702Astructure 700A. In one embodiment, the etch stop layer 112 and theentirety of the barrier layer 108, including the delta doped region 110,in the portion of the T-shaped gate trench 604 not covered by the gatespacers 602 may be removed by a conventional etching process selectiveto the channel layer 106 such as, for example, RIE. The outer edges ofthe T-shaped gate region 702A may be self-aligned to the barrier layer108, including the delta doped region 110, resulting in an effectivegate length L_(geff) that may be equal to the physical gate lengthL_(gp). In other words, there may be available electrons present in theregions below the gate spacers 602 that border the T-shaped gate region702A.

Referring now to FIG. 7B, a gate dielectric layer 702B and a gateconductor 704B may be deposited and planarized in the T-shaped gateregion 702A (FIG. 7A) to form a T-shaped gate structure 706B on theIII-V MOSFET structure 700B. The gate dielectric layer 702B may becomposed of a dielectric material having a dielectric constant ofgreater than approximately 4.0; such a dielectric material is referredto hereafter as a high-k dielectric material. The gate dielectric layer702B may be composed of a high-k dielectric material having a dielectricconstant of greater than approximately 7.0. In a preferred embodiment,the gate dielectric layer 702B may be composed of a high-k dielectricmaterial having a dielectric constant of greater than approximately10.0. The dielectric constants mentioned herein are relative to avacuum, unless otherwise stated. The gate dielectric layer 702B may becomposed of a high-k dielectric material including, but not limited to:an oxide, nitride, oxynitride and/or silicates including metalsilicates, aluminates, titanates, and nitrides. In one embodiment, thegate dielectric layer 702B may be composed of HfO₂, ZrO₂, Al₂O₃, TiO₂,La₂O₃, SrTiO₃, LaAlO₃, Y₂O₃, a pervoskite oxide, HfSiO_(z), HfAlO_(z),or HfAlO_(a)N_(b). The gate dielectric layer 702B, may be formedutilizing a conventional deposition process including, but not limitedto, MBE, CVD, PECVD, ALD, evaporation, PVD, chemical solutiondeposition, and other like deposition processes.

The thickness of the gate dielectric layer 702B may vary depending onthe deposition technique employed in forming the same as well as thecomposition and number of dielectrics of the gate dielectric layer 702B.Typically, the gate dielectric layer 702B may have a thickness ofapproximately 0.5 nm to approximately 20 nm.

The gate conductor 704B may be composed of any conductive material suchas, for example: polysilicon, polysilicon germanium, conductive metals,conductive metal alloys, conductive silicides, conductive nitrides, andcombinations or multilayers thereof. When metallic-containing gateconductors are employed, the metallic gate conductor can be doped so asto shift the workfunction of the gate conductor. Illustrative examplesof dopant ions include As, P, B, Sb, Bi, Al, Ga, Ti, or mixturesthereof. The same dopants may be used with the polysilicon or polySiGementioned above. In a preferred embodiment, the gate conductor 704B is aconductive metal such as Al, Pt, Au, W, and Ti. The gate conductor 704Bmay be formed by a conventional deposition process such as, for example,CVD, PECVD, PVD, plating, thermal or ebeam evaporation, and sputtering.

In one embodiment, after the gate dielectric layer 702B and the gateconductor 704B are deposited they may be planarized using a conventionalprocess such as, for example, CMP, so that an upper surface of theT-shaped gate structure 706B is substantially flush with the uppersurface of the dielectric regions 502.

Referring now to FIG. 8A, and in another embodiment, a structure 800Ashows an undoped region 802A epitaxially grown on the exposed uppersurface of the channel layer 106 to form a T-shaped gate region 804A.The undoped region 802A may be composed of the same material as thebarrier layer 108 and grown through an epitaxial growth process that isselective to the channel layer 106 (i.e., does not result in epitaxialgrowth on the dielectric regions 502, the gate spacers 602, or thebarrier layer 108). The undoped region 802A may have a thickness ofapproximately 1 nm to approximately 2 nm. The outer edges of theT-shaped gate region 804A may be self-aligned to the barrier layer 108,including the delta doped region 110, resulting in an effective gatelength L_(geff) that may be equal to the physical gate length L_(gp). Inother words, there may be available electrons present in the regionsbelow the gate spacers 602 that border the T-shaped gate region 804A.

Referring now to FIG. 8B, a III-V MOS-HEMT structure 800B may be formedby depositing a gate dielectric layer 802B and a gate conductor 804B inthe T-shaped gate region 804A (FIG. 8A) and on the undoped region 802Ato form a T-shaped gate structure 806B using the same processes andtechniques described above with reference to FIG. 7B. The gatedielectric layer 802B and gate conductor 804B may be substantiallysimilar to the gate dielectric layer 702B and the gate conductor 704B asdescribed above with reference to FIG. 7B.

As described above, preferred embodiments of the present inventionprovide for self-aligned overlapped III-V MOS-HEMTs and III-V MOSFETsusing formation methods that avoid the problems associated with ionimplantation in III-V devices such as strain relaxation and insufficientdiffusion or activation of implanted ions.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a,” “an,” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. The descriptions of the various embodiments of the presentinvention have been presented for purposes of illustration, but are notintended to be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiment, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdisclosed herein.

1. A method of forming a semiconductor device, comprising the steps of:forming a III-V compound semiconductor-containing heterostructure havingat least one layer; and forming a T-shaped gate structure using a gatereplacement process, the T-shaped gate structure having a bottom surfacesubstantially below an upper surface of the III-V compoundsemiconductor-containing heterostructure and an upper surface above theIII-V compound semiconductor-containing heterostructure.
 2. The methodof claim 1, wherein the forming III-V compound semiconductor-containingheterostructure comprises: forming a buffer layer on a semiconductorsubstrate; forming a channel layer on the buffer layer; forming abarrier layer on the channel layer; and forming an etch stop layer onthe barrier layer.
 3. The method of claim 2, further comprising forminga delta-doped region above a bottom surface of the barrier layer bydoping the region with an element from Group IV, II, or VI of thePeriodic Table of Elements.
 4. The method of claim 1, wherein the uppersurface of the T-shaped gate structure is longer than the bottomsurface.
 5. The method of claim 1, further comprising forming gatespacers on an upper surface of the III-V compoundsemiconductor-containing heterostructure adjacent to and contacting avertical portion of the T-shaped gate structure, the gate spacers havingan outer side that is substantially flush with an outer side of theT-shaped gate structure.
 6. The method of claim 1, further comprisingforming raised source-drain (RSD) regions on the upper surface of theIII-V compound semiconductor-containing heterostructure adjacent to andcontacting the gate spacers.
 7. The method of claim 1, furthercomprising forming dielectric regions on the RSD regions, the dielectricregions contacting a portion of the gate spacers and a portion of theouter side of the T-shaped gate structure.
 8. The method of claim 1,further comprising forming an undoped region below the bottom surface ofthe T-shaped gate structure on a layer of the III-V compoundsemiconductor containing-heterostructure.
 9. A method of forming asemiconductor device, comprising the steps of: forming a III-V compoundsemiconductor-containing heterostructure having at least one layer;forming a T-shaped gate structure using a gate replacement process, theT-shaped gate structure having a bottom surface substantially below anupper surface of the III-V compound semiconductor-containingheterostructure and an upper surface above the III-V compoundsemiconductor-containing heterostructure; forming gate spacers on theupper surface of the III-V compound semiconductor-containingheterostructure adjacent to and contacting a vertical portion of theT-shaped gate structure, the gate spacers having an outer side that issubstantially flush with an outer side of the T-shaped gate structure;forming raised source-drain (RSD) regions on the upper surface of theIII-V compound semiconductor-containing heterostructure adjacent to andcontacting the gate spacers; and forming dielectric regions on an uppersurface of the RSD regions, the dielectric regions contacting the gatespacers and contacting the outer side of the T-shaped gate structure andhaving an upper surface that is substantially flush with the uppersurface of the T-shaped gate structure.
 10. The method of claim 9,wherein the forming III-V compound semiconductor-containingheterostructure comprises: forming a buffer layer on a semiconductorsubstrate; forming a channel layer on the buffer layer; forming abarrier layer on the channel layer; and forming an etch stop layer onthe barrier layer.
 11. The method of claim 10, further comprisingforming a delta-doped region above a bottom surface of the barrier layerby doping the region with an element from Group IV, II, or VI of thePeriodic Table of Elements.
 12. The method of claim 9, wherein the uppersurface of the T-shaped gate structure has a longer length than thebottom surface.
 13. The method of claim 9, wherein the forming aT-shaped gate structure comprises forming a gate dielectric layer and agate conductor thereon.
 14. The method of claim 9, further comprisingforming an undoped region below the bottom surface of the T-shaped gatestructure on a layer of the III-V compound semiconductorcontaining-heterostructure.
 15. A semiconductor structure, comprising: aIII-V compound semiconductor-containing heterostructure having at leastone layer; a T-shaped gate structure having a bottom surface on achannel layer substantially below an upper surface of the III-V compoundsemiconductor-containing heterostructure and an upper surface above theIII-V compound semiconductor-containing heterostructure; gate spacers onthe upper surface of the III-V compound semiconductor-containingheterostructure adjacent to and contacting a vertical portion of theT-shaped gate structure, the gate spacers having an outer side that issubstantially flush with an outer side of the T-shaped gate structure;and raised source-drain (RSD) regions on the upper surface of the III-Vcompound semiconductor-containing heterostructure adjacent to andcontacting the gate spacers.
 16. The structure of claim 15, furthercomprising dielectric regions on an upper surface of the RSD regions,the dielectric regions contacting the gate spacers and contacting theouter side of the T-shaped gate structure, the dielectric regions havingan upper surface that is substantially flush with the upper surface ofthe T-shaped gate structure.
 17. The structure of claim 15, wherein theIII-V compound semiconductor-containing heterostructure comprises: abuffer layer formed on a semiconductor substrate; a channel layer on thebuffer layer; a barrier layer on the channel layer; and an etch stoplayer on the barrier layer.
 18. The structure of claim 17, furthercomprising a delta-doped region above a bottom surface of the barrierlayer containing dopant elements from Group IV, II, or VI of thePeriodic Table of Elements.
 19. The structure of claim 15, furthercomprising an undoped region beneath the bottom surface of the T-shapedgate structure on a layer of the III-V compound semiconductor-containingheterostructure.
 20. The structure of claim 15, wherein the T-shapedgate structure is comprised of a gate conductor formed on a gatedielectric layer.